DESIGN AND DEVELOP LOW-POWER MEMORY CONTROLLER FOR GAIN CELL-EMBEDDED DYNAMIC RANDOM-ACCESS MEMORY CELL USING INTELLIGENT CLOCK GATING

Abstract

This article focuses on the design and development of a low-power memory controller that contains an intelligent clock gating (ICG) circuit for use with gain cell-embedded dynamic random-access memory (GC-eDRAM) cells. ICG refers to the process by which a memory controller determines when to start or stop the clock. A graphics processing unit (GPU) of today must have a reliable memory controller in order to successfully manage data transactions. The GC-eDRAM is a crucial component of today's GPUs, and this component is required for the GPU to function properly. The proposed design for the memory controller makes use of the ICG circuit in order to achieve maximum efficiency in terms of power consumption. The ICG circuit is responsible for the intelligent regulation of clock signals, which helps to limit the amount of wasteful switching activity and dynamic power waste. The ICG circuit guarantees that power is saved without affecting the performance of the memory controller by selectively gating the clock signal to the memory cells during times in which the memory cells are not being actively used. To enable customizable data transaction burst durations, the design and development process must include the AXI4 full memory-mapped interface protocol. In addition, additional registers and data FIFOs have been included into the design in order to accommodate the variable burst lengths that are made available by the AXI4 protocol. The proposed low-power memory controller architecture is put to the test with an examination of both its logic use and dynamic power consumption in order to determine how effective it is. The designs of the memory controllers with and without the ICG circuit are compared in order to demonstrate the advantages of adding the ICG circuit, which include a decrease in the amount of power that is used by the system and an improvement in its overall performance. The findings indicate that the low-power memory controller that incorporates the ICG circuit is capable of achieving 11% power reductions in comparison to the existing design.