Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers-Reference-Cited by-同舟云学术

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Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

Published:2019-01 Issue:1 Volume:54 Page:65-74
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Megawer Karim M.^ORCID,Elkholy Ahmed^ORCID,Gamal Ahmed Mostafa^ORCID,Elmallah Ahmed,Kumar Hanumolu Pavan

Funder

Analog Devices

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8613098/08486730.pdf?arnumber=8486730

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering;IEEE Journal of Solid-State Circuits;2024-07

2. A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator;IEEE Journal of Solid-State Circuits;2024

3. Design of Clock Multiplier using Modified Voltage-controlled Delay Line;2023 IEEE 15th International Conference on Computational Intelligence and Communication Networks (CICN);2023-12-22

4. Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process;Electronics;2023-06-26

5. Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art;Chip;2023-06

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