Affiliation:
1. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea
2. SKAIChips, Suwon 16419, Republic of Korea
Abstract
In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm2. The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference6 articles.
1. Reuben, J., Anuroop, A., and Kittur, H.M. (2012, January 21–22). Clock frequency doubler circuit for multiple frequencies and its application in a CDN to reduce power. Proceedings of the 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET), Nagercoil, India.
2. Hsueh, Y.-L. (2014, January 9–13). 28.2 A 0.29 mm2 frequency synthesizer in 40 nm CMOS with 0.19 psrms jitter and <−100 dBc reference spur for 802.11ac. Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA.
3. Voltage Controlled Delay Line with PFD for Delay Locked Loop in CMOS 90 nm Technology;Patel;IJRECT,2014
4. A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS;Raja;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2016
5. A 0.33–1 GHz Open-Loop Duty Cycle Corrector with Digital Falling Edge Modulator;Kang;IEEE Trans. Circuits Syst. II Exp. Briefs,2018
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