7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur
Author:
Affiliation:
1. University of Macau,Macau,China
2. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China
Funder
Technology Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454291.pdf?arnumber=10454291
Reference6 articles.
1. A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
2. A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs
3. A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer
4. A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques
5. 2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL
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