2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL-Reference-Cited by-同舟云学术

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2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL

Published:2016-01 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Huang Zhiqiang,Jiang Bingwei,Li Lianming,Luong Howard Cam

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7405163/7417881/7417896.pdf?arnumber=7417896

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