A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ-Reference-Cited by-同舟云学术

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

Published:2023-01 Issue:1 Volume:58 Page:279-290
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lee Daewoong¹^ORCID,Baek Jaehyeok¹,Kwon Hye-Jung¹,Kwon Dae-Hyun¹,Cho Chulhee¹^ORCID,Kim Sang-Hoon¹,An Donggun¹^ORCID,Chang Chulsoon²,Lim Unhak¹,Im Jiyeon¹,Sung Wonju¹,Kim Hye-Ran¹,Park Sun-Young¹,Kim Hyoung-Joo¹,Seol Hoseok¹,Kim Juhwan¹,Shin Jungbum¹,Kang Gil-Young¹,Kim Yong-Hun¹,Kim Sooyoung¹,Park Wansoo³,Kim Seok-Jung¹,Lee Chan-Yong¹,Lee Seungseob¹,Park Tae-Hoon²,Oh Chi-Sung¹^ORCID,Ban Hyodong¹,Ko Hyungjong¹,Song Hoyoung¹,Oh Tae-Young¹,Hwang Sang-Joon¹,Oh Kyung-Suk³,Choi Jung-Hwan¹^ORCID,Lee Jooyoung¹

Affiliation:

1. Memory Division, Samsung Electronics, Hwaseong, South Korea

2. DRAM PIE1Group, Samsung Electronics, Hwaseong, South Korea

3. PKG Design Team, Samsung Electronics, Hwaseong, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9999561/09968075.pdf?arnumber=9968075

Reference23 articles.

1. An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling

2. A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

3. A 1.2 V 64 Gb 341 GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control;cho;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2018

4. Broadband esd protection circuits in cmos technology

5. A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

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1. 13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

2. An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2024

3. A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

4. A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces;IEEE Journal of Solid-State Circuits;2023-08

5. A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application;IEEE Journal of Solid-State Circuits;2023-01