CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out-Reference-Cited by-同舟云学术

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

Published:2022-06-13 Issue: Volume: Page:
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Container-title:2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
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Author:

Singh Abhairaj¹,Zahedi Mahdi¹,Shahroodi Taha¹,Gupta Mohit²,Gebregiorgis Anteneh¹,Komalan Manu²,Joshi Rajiv V.³,Catthoor Francky²,Bishnoi Rajendra¹,Hamdioui Said¹

Affiliation:

1. Computer Engineering Laboratory,TU Delft,The Netherlands

2. IMEC Leuven,Belgium

3. IBM Thomas J. Watson Research Centre,Yorktown,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9869844/9869845/09869993.pdf?arnumber=9869993

Reference12 articles.

1. A crossbar array of magnetoresistive memory devices for in-memory computing

2. Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

3. STT-MRAM Design Technology Co-optimization for Hardware Neural Networks

4. A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network

5. Read disturb fault detection in STT-MRAM

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