MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array-Reference-Cited by-同舟云学术

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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array

Published:2023-12-04 Issue: Volume: Page:1-5
ISSN:
Container-title:2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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Author:

Escuin Carlos¹,García-Redondo Fernando²,Zahedi Mahdi³,Ibáñez Pablo⁴,Monreal Teresa⁵,Viñals Víctor²,Llabería José María⁵,Myers James²,Ryckaert Julien¹,Biswas Dwaipayan¹,Catthoor Francky¹

Affiliation:

1. IMEC,Leuven,Belgium

2. IMEC,Cambridge,UK

3. Delft University of Technology,Department of Quantum and Computer Engineering,Delft,The Netherlands

4. Universidad de Zaragoza,Dept. Informática e Ingeniería de Sistemas - I3A,Zaragoza,Spain

5. Universitat Politècnica de Catalunya,Barcelona,Spain

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10382705/10382711/10382874.pdf?arnumber=10382874

Reference13 articles.

1. RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!

2. STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes

3. Improved Switching Stability and the Effect of an Internal Series Resistor in HfO2/TiOx Bilayer ReRAM Cells

4. Deep Residual Learning for Image Recognition

5. HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing

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