STT-MRAM Design Technology Co-optimization for Hardware Neural Networks
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8601505/8614478/08614560.pdf?arnumber=8614560
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. On-Device Continual Learning With STT-Assisted-SOT MRAM-Based In-Memory Computing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects;Frontiers in Neuroscience;2024-04-10
3. Area-Aware Optimization of MRAM Crossbar Array Bit-Cell for In-Memory Computing;IEEE Transactions on Electron Devices;2023-09
4. An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-06
5. Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05
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