An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI-Reference-Cited by-同舟云学术

An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI

Published:2023-06 Issue:6 Volume:70 Page:1871-1875
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Li Yi¹^ORCID,Chen Jia²,Wang Linfang¹^ORCID,Zhang Woyu¹,Guo Zeyu¹,Wang Jun¹,Han Yongkang³,Li Zhi¹,Wang Fei¹,Dou Chunmeng¹^ORCID,Xu Xiaoxin¹^ORCID,Yang Jianguo¹^ORCID,Wang Zhongrui²,Shang Dashan¹^ORCID

Affiliation:

1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

2. ACCESS–AI Chip Center for Emerging Smart Systems, InnoHK Centers, Hong Kong Science Park, Hong Kong

3. Zhejiang Lab, Hangzhou, China

Funder

National Key Research and Development Program and NSFC of China

National Natural Science Foundation of China

Strategic Priority Research Program of the Chinese Academy of Sciences

Major Scientific Research Project of Zhejiang Lab

Hong Kong RGC

ACCESS—AI Chip Center for Emerging Smart Systems, sponsored by Innovation and Technology Fund (ITF), Hong Kong, SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10138208/10004708.pdf?arnumber=10004708

Reference15 articles.

1. STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

2. 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

3. STT-MRAM Design Technology Co-optimization for Hardware Neural Networks

4. XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

5. In-sensor reservoir computing system for latent fingerprint recognition with deep ultraviolet photo-synapses and memristor array

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