Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node-Reference-Cited by-同舟云学术

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Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Published:2018-12 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Electron Devices Meeting (IEDM)
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Author:

Sakhare S.,Perumkunnil M.,Bao T. Huynh,Rao S.,Kim W.,Crotti D.,Yasin F.,Couet S.,Swerts J.,Kundu S.,Yakimets D.,Baert R.,Oh HR.,Spessot A.,Mocuta A.,Kar G. Sankar,Furnemont A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8601505/8614478/08614637.pdf?arnumber=8614637

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Nonvolatile Memristive Materials and Physical Modeling for In‐Memory and In‐Sensor Computing;Small Science;2024-01-22

2. Impact of Off-Axis External Magnetic Field Perturbation on the Write Error Slopes of Perpendicular STT-RAM Cell: Micromagnetic Study;IEEE Magnetics Letters;2024

3. Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01

4. Resistive Switching Properties in Memristors for Optoelectronic Synaptic Memristors: Deposition Techniques, Key Performance Parameters, and Applications;ACS Applied Electronic Materials;2023-12-29

5. Artificial Neuron Devices;Chemical Reviews;2023-11-17

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