A 0.42–3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition-Reference-Cited by-同舟云学术

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A 0.42–3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition

Published:2020-06 Issue:6 Volume:67 Page:974-978
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Son Kyung-Sub^ORCID,An Taek-Joon,Moon Yong-Hwan^ORCID,Kang Jin-Ku^ORCID

Funder

National Research Foundation of Korea

Ministry of Trade, Industry and Energy

Korea Semiconductor Research Consortium Support Program for the Development of the Future Semiconductor Device

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9103104/08758335.pdf?arnumber=8758335

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD;Microelectronics Journal;2024-09

2. 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

3. CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

4. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

5. A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation;International Journal of Circuit Theory and Applications;2023-01-04

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