A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Abstract

SummaryThis paper reports a bang‐bang clock and data recovery circuit (BBCDR) with an ultra‐wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6‐to‐38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate‐current‐mismatch technique. Moreover, we accurately obtain an eight‐phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter‐based phase interpolator. A 65‐nm prototype of the developed BBCDR occupies an area of 0.07 mm2 and attains a bit error rate of less than 10−12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32‐Gb/s non‐return‐zero input, thus leading to 0.769‐pJ/bit energy efficiency.