Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives-Reference-Cited by-同舟云学术

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Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives

Published:2014-12 Issue:12 Volume:22 Page:2499-2512
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Alioto Massimo,Esseni David

Funder

EU through the STEEPER project

Italian MIUR through the Futuro in Ricerca 2010

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/6963544/06754164.pdf?arnumber=6754164

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel gate over source-channel overlap dual-gate TFET with insulator pocket and lateral source contact for optimizing subthreshold characteristic;Microelectronics Journal;2024-09

2. A Novel Gate Over Source-Channel Overlap Dual-Gate Tfet with Insulator Pocket and Lateral Source Contact for Optimizing Subthreshold Characteristic;2024

3. Design of Negative Capacitance based Dopantfree Junctionless Nanowire Tunnel FET for Analog and Linearity Analysis;2023 8th International Conference on Communication and Electronics Systems (ICCES);2023-06-01

4. Drain Charge Technique in TFET for Analog Transconductor Application;Silicon;2022-11-03

5. Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD;Silicon;2022-01-07

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