Design of Negative Capacitance based Dopantfree Junctionless Nanowire Tunnel FET for Analog and Linearity Analysis-Reference-Cited by-同舟云学术

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Design of Negative Capacitance based Dopantfree Junctionless Nanowire Tunnel FET for Analog and Linearity Analysis

Published:2023-06-01 Issue: Volume: Page:
ISSN:
Container-title:2023 8th International Conference on Communication and Electronics Systems (ICCES)
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Author:

Latief Esha¹,Kumar Pradeep¹,Anand Sunny²,Solay Leo Raj¹

Affiliation:

1. Amity University Uttar Pradesh,Amity School of Engineering and Technology,Dept. of ECE,Noida,India

2. HCL Technologies,Technical Lead,Noida

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10192571/10192589/10192700.pdf?arnumber=10192700

Reference27 articles.

1. III-V Heterostructure Nanowire Tunnel FETs

2. Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

3. Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity

4. Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric

5. Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives

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