A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector-Reference-Cited by-同舟云学术

A 188fs_rms-Jitter and −243d8-FoM_jitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Hwang Chanwoong¹,Park Hangi¹,Seong Taeho¹,Choi Jaehyouk¹

Affiliation:

1. KAIST,Daejeon,Korea

Funder

Samsung Electronics

IC Design Education Center

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731646.pdf?arnumber=9731646

Reference10 articles.

1. A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

2. A 365fsrms-Jitter and ?63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-NDpll Using a DTC Second/Third-Order Nonlinearity Cancelation and a Probability-Density-Shaping $\Delta\Sigma$ M;park;ISSCC,2021

3. A Fractional-$N$ PLL With Space–Time Averaging for Quantization Noise Reduction

4. 29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur

5. 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels

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