7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and −54.4dBc Spurs Under 50mV Supply Noise
Author:
Affiliation:
1. University of Illinois,Urbana,IL
Funder
Semiconductor Research Corporation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454445.pdf?arnumber=10454445
Reference6 articles.
1. A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
2. A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
3. A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
4. A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
5. A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
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