A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur-Reference-Cited by-同舟云学术

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

Published:2022-02-20 Issue: Volume: Page:
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Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Tsai Tsung-Hsien¹,Sheen Ruey-Bin¹,Hsu Sheng-Yun¹,Chang Ya-Tin¹,Chang Chih-Hsien¹,Staszewski Robert Bogdan²

Affiliation:

1. TSMC,Hsinchu,Taiwan

2. University College Dublin,Dublin,Ireland

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731676.pdf?arnumber=9731676

Reference7 articles.

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2. A 23.6-38.3GHz Low-Noise PLL with Digital Ring Oscillator and Multi-Ratio Injection-Locked Dividers for Millimeter-Wave Sensing

3. A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture

4. A hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment with 0.6?s Settling, 0.619 ps Integrated Jitter and -240.5 dB FoM in 7-nm FinFET;tsai;IEEE SSC-L,2020

5. A 104fsrms-Jitter and -61 dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique;kim;ISSCC,2021

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