A 0.2-to-39.2GHz 66.2-fs Jitter and −71.3dBc Spur Sub-Sampling PLL Using DAC-Based Constant Control Voltage Compensator and Quad-Mode 2nd Harmonic Filtering Oscillator
Author:
Affiliation:
1. University of Electronic Science and Technology of China,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10599936/10599927/10599960.pdf?arnumber=10599960
Reference10 articles.
1. A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
2. A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
4. A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation
5. A 66fsrms jitter 12.8-to-15.2GHz fractional-N bang-bang PLL with digital frequency-error recovery for fast locking;Santiccioli;IEEE ISSCC Dig. Tech. Papers,2020
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