A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors

Author:

Chen Denis Guangyin,Tang Fang,Law Man-Kay,Zhong Xiaopeng,Bermak Amine

Funder

Hong Kong Research

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 35 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of a Rail-to-rail 12-Bit 2.5-MSPS SAR ADC with Low-area on 180nm CMOS Process;2024 Tenth International Conference on Communications and Electronics (ICCE);2024-07-31

2. Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. A linearity improvement method for CIS column-parallel SAR ADC using two-step conversion;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

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