A linearity improvement method for CIS column-parallel SAR ADC using two-step conversion
Author:
Affiliation:
1. Delft University of Technology,Electronic Instrumentation Laboratory,Delft,The Netherlands
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268814.pdf?arnumber=10268814
Reference7 articles.
1. Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits
2. A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors
3. 6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs
4. An offset calibration technique for CIS columnparallel SAR ADCs using memory;lee;Proc IS& T Int'l Symp on Electronic Imaging Imaging Sensors and Systems,2022
5. A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs
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