Enhancement in Capacitance and Transconductance in 90 nm nFETs with HfO2-ZrO2 Superlattice Gate Stack for Energy-efficient Cryo-CMOS
Author:
Affiliation:
1. Electrical Engineering and Computer Sciences
2. University of California,Material Sciences and Engineering,Berkeley
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019496.pdf?arnumber=10019496
Reference17 articles.
1. Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit
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3. Large Injection Velocities in Highly Scaled, Fully Depleted Silicon on Insulator Transistors
4. Analysis of Carrier Transport in Short-Channel MOSFETs
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1. Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
2. Demonstration of EOT-Scaled FinFET Based on Thickness-Proportion Controlled HZH Superlattice Gate Stacks With Improved Thermal Stability (≥ 450 °C);IEEE Electron Device Letters;2024-07
3. High-Speed and Low-Power Ferroelectric HfO₂/ZrO₂ Superlattice FinFET Memory Device Using AlON Interfacial Layer;IEEE Transactions on Electron Devices;2024-06
4. Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack;IEEE Electron Device Letters;2024-03
5. The Future is Frozen: Cryogenic CMOS for High-Performance Computing (Invited);Chip;2023-12
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