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Minimum Power Test Pattern Generator for Testing VLSI Circuits

  • Published:2022-04-21 Issue: Volume: Page:
  • ISSN:
  • Container-title:2022 6th International Conference on Devices, Circuits and Systems (ICDCS)
  • language:
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Author:

Govindaraj V.1,Manoharan K.2,Prabha K. Lakshmi3,Dhanasekar S.4,Sreekanth K5

Affiliation:

1. Dr.N.G.P Institute of Technology,Department of ECE,Coimbatore,India

2. Sri Eshwar College of Engineering,Department of ECE,Coimbatore,India

3. SNS College of Technology,Department of Biomedical Engineering,Coimbatore,India

4. Simulus Automation Pvt Ltd,ASIC Design and Verification Engineer,Chennai,India

5. PSG Polytechnic College,Department of ECE,Coimbatore,India

Publisher

IEEE

Reference24 articles.

1. iFill

2. Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

3. Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;anita,0

4. Maximum common substructure-based Tversky index: an asymmetric hybrid similarity measure

5. An Improved Low Transition Test Pattern Generator for Low power Applications;govindaraj;Design Automation for Embedded Systems,2017

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1. Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture;IETE Journal of Research;2024-05-20

2. Regression Analysis Based Circuit Power Estimation Technique;2023 International Conference on Evolutionary Algorithms and Soft Computing Techniques (EASCT);2023-10-20

3. A Novel Test Pattern Optimization Method Using Recurrent Neural Network;Journal of Circuits, Systems and Computers;2023-09-22

4. Test Pattern Generation in BIST Architecture Using One-Hot Encoding;2023 4th International Conference on Smart Electronics and Communication (ICOSEC);2023-09-20

5. Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network;Journal of Electronic Testing;2023-08
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