A Novel Test Pattern Optimization Method Using Recurrent Neural Network

Abstract

Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS’89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage.