A Graph Partitioning Approach to Optimize Test Patterns
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-64847-2_14
Reference18 articles.
1. Pon, S.A., Jeyalakshmi, V.: Analysis of switching activity in various implementation of combinational circuit. In: 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS), pp. 115–121 (2020)
2. Maity, H., Khatua, K., Chattopadhyay, S., Sengupta, I., Patankar, G., Bhattacharya, P.: A new test vector reordering technique for low power combinational circuit testing. In: International Symposium on Devices, Circuits and Systems (ISDCS), pp. 1–6 (2020)
3. Maity, H., Chattopadhyay, S., Sengupta, I., Bhattacharya, P., Patankar, G.: An improved test pattern reordering framework targeting test power reduction. In: IEEE International Test Conference India (ITC India), pp. 1–6 (2021)
4. Porto, G., Butzen, S., Franco, D.T.: Exploring BDDs to reduce test pattern set. In: 18th IEEE Latin American Test Symposium (LATS), pp. 1–4 (2017)
5. Song, T., et al.: Pattern reorder for test cost reduction through improved SVMRANK algorithm, IEEE Accesse 8, 147965–147972 (2020)
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