Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture
Author:
Affiliation:
1. Department ECE, Dr NGP Institute of Technology, Coimbatore, 641048, India
2. Department of ECE, Sri Eshwar College of Engineering, Coimbatore, 641202, India
Publisher
Informa UK Limited
Link
https://www.tandfonline.com/doi/pdf/10.1080/03772063.2024.2352146
Reference18 articles.
1. P. Girard C. Landrault S. Pravossoudovitch and D. Severac “Reducing power consumption during test application by test vector ordering ” IEEE International Symposium on Circuits and Systems CD-ROM Monterey USA 1–3 June 1998.
2. J. P. Anita. “Investigation on test pattern Generation and test power reduction techniques for multiple stuck at faults. Ph.D. dissertation ” in Department of Electronics and Communication Engineering in Amrita School of Engineering Coimbatore 2013.
3. Machine Learning Based Power Estimation for CMOS VLSI Circuits
4. BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm
5. Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation
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