Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/8302609/07589036.pdf?arnumber=7589036
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An in-Array Build-In Self-Test Scheme for Embedded SRAM Array;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08
2. Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture;IETE Journal of Research;2024-05-20
3. Efficient weight-based segmentation of scan-chains using NLFSR;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14
4. ASIC vs FPGA based Implementations of Built-In Self-Test;International Journal of Advanced Natural Sciences and Engineering Researches;2023-07-13
5. Low-power test pattern generator using modified LFSR;Aerospace Systems;2023-01-09
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