Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits-Reference-Cited by-同舟云学术

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Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits

Published:2009-09 Issue: Volume: Page:
ISSN:
Container-title:2009 IEEE International Conference on 3D System Integration
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Author:

Weerasekera Roshan,Grange Matt,Pamunuwa Dinesh,Tenhunen Hannu,Zheng Li-Rong

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5290624/5306519/05306541.pdf?arnumber=5306541

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System;Symmetry;2023-02-04

3. Computing and Analyzing Through Silicon Via (TSV) Noise Coupling in 3D-IC Structures;Digital Technologies and Applications;2021

4. On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs;Advances in Science, Technology and Engineering Systems Journal;2017-07

5. Effects of varying the through silicon via liners thickness on their hoop stresses and deflections;The Journal of Engineering;2017-04

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