Effects of varying the through silicon via liners thickness on their hoop stresses and deflections
Author:
Affiliation:
1. University of Electronic Science and Technology of China (UESTC)No. 2006, Xiyuan Avenue, West Hi‐Tech Zone611731ChengduSichuanPeople's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
General Engineering,Energy Engineering and Power Technology,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/joe.2017.0019
Reference29 articles.
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2. GaoX. ChenR. WangX.et al.: ‘Thermo‐mechanical reliability of copper‐filled and polymer‐filled through silicon vias in 3d interconnects’.2013 IEEE 63rd Electronic Components and Technology Conf. (ECTC) 2013 pp.2132–2137
3. ReddyR.R. TannaS. SinghS.G.et al.: ‘TSV noise coupling in 3D IC using guard ring’.2015 Int. 3D Systems Integration Conf. (3DIC) Sendai 2015 pp.TS8.35.1–TS8.35.5
4. BandyopadhyayT. ChatterjeeR. ChungD.et al.: ‘Electrical modeling of through silicon and package vias’.IEEE Int. Conf. on 3D System Integration 2009. 3DIC 2009 2009 pp.1–8
5. Through-Strata-Via (TSV) Parasitics and Wideband Modeling for Three-Dimensional Integration/Packaging
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