Electrical modeling of Through Silicon and Package Vias
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5290624/5306519/05306542.pdf?arnumber=5306542
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review;Materials;2023-12-14
2. Impact of TSV bump and redistribution layer on crosstalk delay and power loss;Memories - Materials, Devices, Circuits and Systems;2023-07
3. Fundamentals and Failures in Die Preparation for 3D Packaging;3D Microelectronic Packaging;2020-11-24
4. Rigorous mathematical model of through‐silicon via capacitance;IET Circuits, Devices & Systems;2018-05
5. Effects of varying the through silicon via liners thickness on their hoop stresses and deflections;The Journal of Engineering;2017-04
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