On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs
Author:
Publisher
ASTES Journal
Subject
Management of Technology and Innovation,Physics and Astronomy (miscellaneous),Engineering (miscellaneous)
Link
http://www.astesj.com/publications/ASTESJ_0203159.pdf
Reference16 articles.
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3. R. Wang, K. Chakrabarty, S. Bhawmik,"At-speed interconnect testing and test-path optimization for 2.5D ICs," in Proc. IEEE VLSI Test Symp. (VTS), 2014, pp. 1-6.
4. R. Weerasekera, M. Grange, et al., "Compact modelling of throughsilicon vias TSV s in three dimensional (3D) integrated circuits," in IEEE Int'l Conf. on 3D System Integration, 2009, pp.1-8.
5. W. Yao, S. Pan, et al., "Modeling and application of multi-port TSV networks in 3-D IC,"IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 4, Apr. 2013., pp. 487-496.
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