Author:
Wang Ran,Chakrabarty Krishnendu,Bhawmik Sudipta
Cited by
6 articles.
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1. The Current Status and Perspective in Testing 3D Stacked ICs;Journal of The Japan Institute of Electronics Packaging;2020-01-01
2. On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs;Advances in Science, Technology and Engineering Systems Journal;2017-07
3. Built-In Self-Test;Testing of Interposer-Based 2.5D Integrated Circuits;2017
4. Test Architecture and Test-Path Scheduling;Testing of Interposer-Based 2.5D Integrated Circuits;2017
5. Post-bond Scan-Based Testing of Interposer Interconnects;Testing of Interposer-Based 2.5D Integrated Circuits;2017