The Current Status and Perspective in Testing 3D Stacked ICs
Author:
Publisher
Japan Institute of Electronics Packaging
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/jiep/23/1/23_32/_pdf
Reference18 articles.
1. 2) K. Kondo, M. Kada, and K. Takahashi, Eds.: "Three-Dimensional Integration of Semiconductors." Springer International Publishing, 2015
2. 3) T. Lu, C. Serafy, Z. Yang, S. K. Samal, S. K. Lim, and A. Srivastava: "TSV-Based 3-D ICs: Design Methods and Tools," IEEE Trans. CAD, Vol. 36, No. 10, pp. 1593–1619, Oct. 2017
3. 5) E. J. Marinissen: "Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs," Proc. Design, Automation & Test in Europe Conf. & Exhibition (DATE), pp. 1277–1282, 2012
4. 6) B. Noia and K. Chakrabarty: "Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs," Springer, 2014
5. 7) E. J. Marinissen, T. McLaurin, and H. Jiao: "IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs," Proc. 21th IEEE European Test Symposium (ETS), 2016, pp. 1–10
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