Computing and Analyzing Through Silicon Via (TSV) Noise Coupling in 3D-IC Structures
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-73882-2_149
Reference23 articles.
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2. Erasekera R, Grange M, Pamunuwa D, Tenhunen H, Zheng L (2009) Compact modeling of through-silicon vias (TSVs) in three dimensional (3-D) integrated circuit. In: Proceedings of IEEE international conference on 3D system integration (3D IC), San Francico, USA
3. Kim D, Mukhopadhyay S, Lim S (2009) TSV aware interconnect length and power prediction for 3D stacked ICs. In: IEEE international interconnect technology conference, pp 26–28
4. Salah K (2015) A TSV to TSV, A TSV to metal interconnects, and A TSV to active device coupling capacitance: analysis and recommendation. In: 10th international conference on design & technology systems in nanoscale era, pp 1–2
5. Cadix L, Fuchs C, Rousseau M, Leduc P, Chaabouni H, Thuaire A, Sillon N (2010) Integration and frequency dependent parametric modeling of through silicon via involved in high density 3D chip stacking. ECS Trans 33(12):1–21
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