Layout guidelines for optimized ESD protection diodes-Reference-Cited by-同舟云学术

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Layout guidelines for optimized ESD protection diodes

Published:2007-09 Issue: Volume: Page:
ISSN:
Container-title:2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
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Author:

Bhatia Karan,Rosenbaum Elyse

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4401721/4401722/04401727.pdf?arnumber=4401727

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Current Injection Effect on ESD Behaviors of the Parasitic Bipolar Transistors inside P+/N-well diode;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

2. Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections;Microelectronics Reliability;2021-08

3. Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications;Microelectronics Reliability;2012-06

4. Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process;Microelectronics Reliability;2009-06

5. Investigation of diode geometry and metal line pattern for robust ESD protection applications;Microelectronics Reliability;2008-10

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