Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process-Reference-Cited by-同舟云学术

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Published:2009-06 Issue:6 Volume:49 Page:650-659
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Hsiao Yuan-Wen,Ker Ming-Dou

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference22 articles.

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4. Morishita Y. A PNP-triggered SCR with improved trigger techniques for high-speed I/O ESD protection in deep sub-micron CMOS LSIs. In: Proceedings of the EOS/ESD symposium; 2005. p. 400–6.

5. Kang M, Song KW, Chung H, Kim J, Lee YT, Kim C. SCR-based ESD protection for high bandwidth DRAMs. In: Proceedings of the IEEE asian solid-state circuits conference; 2007. p. 208–11.

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