3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs-Reference-Cited by-同舟云学术

3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs

Published:2023-12 Issue:2 Volume:9 Page:116-123
ISSN:2329-9231
Container-title:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
language:
Short-container-title:IEEE J. Explor. Solid-State Comput. Devices Circuits

Author:

Mannaa Sara¹^ORCID,Poittevin Arnaud¹,Marchand Cédric¹^ORCID,Deleruyelle Damien¹^ORCID,Deveautour Bastien¹,Bosio Alberto¹^ORCID,O’Connor Ian¹^ORCID,Mukherjee Chhandak²^ORCID,Wang Yifan²,Rezgui Houssem²,Deng Marina²,Maneux Cristell²^ORCID,Müller Jonas³^ORCID,Pelloquin Sylvain³,Moustakas Konstantinos³,Larrieu Guilhem³^ORCID

Affiliation:

1. École Centrale de Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon INL, UMR CNRS 5270, Université de Lyon, Écully, France

2. IMS Laboratory, UMR CNRS 5218, University of Bordeaux, Talence, France

3. LAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, France

Funder

Project Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D

European Union’s Horizon 2020 Research and Innovation Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/6570653/10345396/10232986.pdf?arnumber=10232986

Reference22 articles.

1. The International Roadmap for Devices and Systems: A Beacon for the Electronics Industry

2. Performance-Power Management Aware State-of – the-Art 5nm FinFET Design(5LPE) with Dual CPP from Mobile to HPC Application

3. High Performance 4nm FinFET Platform (4LPE) with Novel Advanced Transistor Level DTCO for Dual-CPP/HP-HD Standard Cells

4. First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro

5. Electro-Thermal Performance Boosting in Stacked Si Gate-all-Around Nanosheet FET With Engineered Source/Drain Contacts

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering;Nano Letters;2024-06-17

2. Energy-efficient Computation-In-Memory Architecture using Emerging Technologies;2023 International Conference on Microelectronics (ICM);2023-12-17