Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering-Reference-Cited by-同舟云学术

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Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering

Published:2024-06-17 Issue:26 Volume:24 Page:7825-7832
ISSN:1530-6984
Container-title:Nano Letters
language:en
Short-container-title:Nano Lett.

Author:

Kumar Abhishek¹,Müller Jonas¹^ORCID,Pelloquin Sylvain¹^ORCID,Lecestre Aurélie¹,Larrieu Guilhem¹^ORCID

Affiliation:

1. LAAS-CNRS, Université de Toulouse, CNRS, 7 Avenue Colonel Roche, 31031 Toulouse, France

Funder

Agence Nationale de la Recherche

H2020 Future and Emerging Technologies

Laboratoire d'analyse et d'architectures des syst?mes, Centre national de la recherche scientifique

Publisher

American Chemical Society (ACS)

Link

https://pubs.acs.org/doi/pdf/10.1021/acs.nanolett.3c04180

Reference32 articles.

1. Ye, P. D.; Ernst, T.; Khare, M. V. IEEE Spectrum. The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore’s Law. https://spectrum.ieee.org/the-nanosheet-transistor-is-the-next-and-maybe-last-step-in-moores-law (accessed 2024–05–30).

2. The future transistors

3. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

4. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

5. Design study of the gate-all-around silicon nanosheet MOSFETs

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