Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/7572233/07552455.pdf?arnumber=7552455
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor with Shallow Trench Isolation and Step Oxide Improvement;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17
2. Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure;Journal of Computational Electronics;2021-09-01
3. An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection;Microelectronics Journal;2021-02
4. Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap;Silicon;2021-01-28
5. ESD-Performance Enhancement of Circular Ultra-High-Voltage 300-V N-Channel Lateral-Diffused MOSFETs by Source/Drain Embedded Schottky Diodes;IEEE Electron Device Letters;2020-11
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