Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor with Shallow Trench Isolation and Step Oxide Improvement-Reference-Cited by-同舟云学术

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Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor with Shallow Trench Isolation and Step Oxide Improvement

Published:2024-03-17 Issue: Volume: Page:1-4
ISSN:
Container-title:2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
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Author:

Liuo Zhibo¹,Chen Tian¹,Li Kui¹,Kan Bo¹,Xiao Li¹,Wang Li¹,Chen Hualun¹

Affiliation:

1. Huahong Semiconductor (Wuxi) Limited,Wuxi,China,214000

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10531806/10531771/10532101.pdf?arnumber=10532101

Reference14 articles.

1. Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors

2. Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application

3. Ultralow ON-Resistance SOI LDMOS With Three Separated Gates and High- $k$ Dielectric

4. 0.13 μm modular BCD technology enable to embedding high density E2PROM, RF and hall sensor suitable for IoT application

5. Effect of Drift-Region Concentration on Hot-Carrier-Induced $R_{\rm on}$ Degradation in nLDMOS Transistors

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