An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection-Reference-Cited by-同舟云学术

An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection

Published:2021-02 Issue: Volume:108 Page:104968
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Sahoo Jagamohan,Mahapatra Rajat,Bhattacharayya Amalendu Bhusan

Publisher

Elsevier BV

Subject

General Engineering

Reference28 articles.

1. A No-snapback LDMOSFET with automotive ESD endurance;Kawamoto;IEEE Trans. Electron. Dev.,2002

2. Layout arrangement concern for lateral DMOS with large geometric array used as output device;Sun;IEEE Trans. Device Mater. Reliab.,2017

3. Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process;Chen;Microelectron. Reliab.,2017

4. How to achieve moving current filament in high voltage LDMOS devices: physical insights & design guidelines for self-protected concepts;Kranthi,2020

5. A novel high voltage ultra-thin SOI-LDMOS with sectional linearly doped drift region;Zhang;IEEE Electron. Device Lett.,2019

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