Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process-Reference-Cited by-同舟云学术

Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process

Published:2017-07 Issue: Volume:74 Page:110-117
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Chen Hung-Wei^ORCID,Chang Mi-Chang

Funder

Vanguard International Semiconductor Corporation, Taiwan

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference25 articles.

1. Safe operating area—A new frontier in LDMOS design;Hower,2002

2. Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits;Chen;IEEE Trans. Device Mater. Reliab.,2012

3. A 20-W stereo class-D audio output stage in 0.6μm BCDMOS technology;Morrow;IEEE J. Solid State Circuits,2004

4. B. Keppens, M. P. J. Mergens, C. S. Trinh, C. C. Russ, B. V. Camp, and K. G. Verhaege, “ESD protection solutions for high voltage technologies,” in Proc. EOS/ESD Symp., 2004, pp. 289–298.

5. Improving the ESD self-protection capability of integrated power NLDMOS arrays;Vashchenko,2010

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