Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap-Reference-Cited by-同舟云学术

Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap

Published:2021-01-28 Issue: Volume: Page:
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Singh Avtar^ORCID,Pandey Chandan Kumar

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/content/pdf/10.1007/s12633-021-00957-0.pdf

Reference26 articles.

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3. Sharma SM, Singh A, Dasgupta S, Kartikeyan MV (2020) A review on the compact modeling of parasitic capacitance: from basic to advanced FETs, J Comput Electron, no. 0123456789, doi: https://doi.org/10.1007/s10825-020-01515-4

4. Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) Nanotube tunneling FET with a Core source for Ultrasteep subthreshold swing: a simulation study. IEEE Trans Electron Devices 66(10):4425–4432. https://doi.org/10.1109/TED.2019.2933756

5. Mukherjee C, Maiti CK (2012) Nanowires - recent advances,, doi: https://doi.org/10.5772/3367

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