Impact of Underlap/Overlap on Source Engineered Tunnel FET-Reference-Cited by-同舟云学术

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Impact of Underlap/Overlap on Source Engineered Tunnel FET

Published:2023-09-01 Issue: Volume: Page:
ISSN:
Container-title:2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS)
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Author:

Shakya Arzoo¹,Mishra Adarsh Kumar²,Bhadauria Tanvi¹,Singh Avtar³,Kaur Amandeep⁴

Affiliation:

1. Jamia Millia Islamia University,Department of Applied Sciences and Humanities,New Delhi,110025

2. ELEX - School of Electronics Devi Ahilya Vishwavidyalaya, University of Indore,Madhya Pradesh

3. SOEEC Adama Science and Technology University,Department of ECE,Adama,Ethiopia

4. Bhaskaracharya College of Applied Sciences, University of Delhi,Department of Instrumentation,New Delhi,110075

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10291170/10291178/10291970.pdf?arnumber=10291970

Reference14 articles.

1. Gate length scaling and threshold voltage control of double-gate MOSFETs

2. Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

3. Atlas User's Manual;SILVACO Inc,2016

4. Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- $k$ Spacer for Low Power Applications

5. Influence of Drain Doping Engineering on the Ambipolar Conduction and High-Frequency Performance of TFETs

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