Fabrication and Individual Addressing of STT-MRAM Bit Array With 50 nm Full Pitch
Author:
Affiliation:
1. Western Digital Research, San Jose, CA, USA
Funder
Western Digital Company
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/20/9762634/09696250.pdf?arnumber=9696250
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1. Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy
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4. High-Performance Shape-Anisotropy Magnetic Tunnel Junctions down to 2.3 nm
5. Integration of 28 nm MTJ for 8~16Gb level MRAM with full investigation of thermal stability;kim;Symp VLSI Technology Dig Tech Papers,2011
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1. Dipole-coupled core-shell perpendicular-shape-anisotropy magnetic tunnel junction with enhanced write speed and reduced crosstalk;Physical Review Applied;2024-04-18
2. Pitch Scaling Prospect of Ultra-Small Magnetic Tunnel Junctions for High-Density STT-MRAM: Effects of Magnetostatic Interference From Neighboring Bits;IEEE Electron Device Letters;2024-02
3. NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector;IEEE Electron Device Letters;2023-04
4. First demonstration of full integration and characterization of 4F² 1S1M cells with 45 nm of pitch and 20 nm of MTJ size;2022 International Electron Devices Meeting (IEDM);2022-12-03
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