NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector-Reference-Cited by-同舟云学术

NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector

Published:2023-04 Issue:4 Volume:44 Page:614-617
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Hiblot Gaspard¹^ORCID,Ravsher Taras¹^ORCID,Loo Roger¹^ORCID,Ramana Bhuvaneshwari Yengula Venkata¹,Canvel Yann¹,Vergel Nathali Franchina¹^ORCID,Fantini Andrea¹,Sharifi Shamin Houshmand¹,Bazzazian Nina¹^ORCID,Ayyad Mustafa¹,Merkulov Alex¹,Kar Gouri Sankar¹,Couet Sebastien¹^ORCID

Affiliation:

1. IMEC, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10081123/10036431.pdf?arnumber=10036431

Reference23 articles.

1. Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond

2. Highly functional and reliable 8 Mb STT-MRAM embedded in 28 nm logic;song;IEDM Tech Dig,2016

3. Implementation of nonlocal model for impact-ionization current in bipolar circuit simulation and application to SiGe HBT design optimization

4. Sub-0.2 V Impact Ionization in Si n-i-p-i-n Diode

5. Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications

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1. NPN Si/SiGe memory selector with non-linearity>10⁵ and ON-current>6MA/cm²;ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC);2023-09-11