Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations-Reference-Cited by-同舟云学术

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Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Memory Workshop (IMW)
language:
Short-container-title:

Author:

Spessot Alessio¹,Salahuddin Shairfe Muhammad¹,Escobar Ricardo¹,Ritzenthaler Romain¹,Xiang Yang¹,Budhwani Rahul¹,Litta Eugenio Dentoni¹,Capogreco Elena¹,Bastos Joao¹,Chen Yangyin²,Naoto Horiguchi¹

Affiliation:

1. imec.,Belgium,3001

2. Western Digital assignee at imec

Funder

Western Digital

Micron

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9779263/9779243/09779308.pdf?arnumber=9779308

Reference20 articles.

1. Optimized material solutions for advanced DRAM peripheral transistors

2. Impact of Mechanical Stress on 3-D NAND Flash Current Conduction

3. DRAM Technology - History & Challenges;cha;IEDM Short Course,0

4. Gate-first high-k/metal gate DRAM technology for low power and high performance products

5. A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate Process

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-Density 3-D NAND Cell Array Design With Hybrid Bonding;IEEE Transactions on Electron Devices;2023-11

2. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits;2022 International Electron Devices Meeting (IEDM);2022-12-03

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