A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate Process-Reference-Cited by-同舟云学术

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A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate Process

Published:2019-12 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Electron Devices Meeting (IEDM)
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Author:

Jang Sung Ho,Yamada Satoru,Lee Kyupil,Lim Junhee,Han Joon,Jang Juyeon,Yeo Jaehyun,Lee Chanmin,Baek Sungkweon,Lee Jaehoon,Lee Jong-Ho

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8971803/8993428/08993517.pdf?arnumber=8993517

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Highly reliable bipolar resistive switching of tantalum oxide-based memory using Al2O3 diffusion barrier layers;Current Applied Physics;2024-05

2. Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application;Japanese Journal of Applied Physics;2024-02-12

3. Machine learning investigation of high-k metal gate processes for dynamic random access memory peripheral transistor;APL Materials;2024-02-01

4. Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications;Science China Information Sciences;2023-09-21

5. Investigation on NBTI Control Techniques of HKMG Transistors for Low-power DRAM applications;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

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