FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits
Author:
Affiliation:
1. imec, Kapeldreef 75,Leuven,Belgium,B-3001
2. Micron
3. SK-Hynix
4. Kioxia
5. Western Digital
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019422.pdf?arnumber=10019422
Reference16 articles.
1. EOT of 0.62 nm and High Electron Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and Annealing at High Temperature
2. Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices
3. Origin of the Flatband-Voltage Roll-Off Phenomenon in Metal/High- $k$ Gate Stacks
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1. Decoupled Plasma Nitridation (DPN) and Postnitridation Annealing (PNA) Treatment for Metal Boundary Effect Reduction;IEEE Transactions on Electron Devices;2024-03
2. Significant Threshold Voltage Lowering Induced by Contact Silicidation Annealing of FinFET;IEEE Transactions on Electron Devices;2023-08
3. Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility;ACS Applied Materials & Interfaces;2023-07-25
4. Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique;Nanomaterials;2023-04-03
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