1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation
Author:
Affiliation:
1. Department of Electrical Engineering, IIT Madras, Chennai, India
2. Fraunhofer-IPMS, CNT, Dresden, Germany
3. GlobalFoundries, Dresden, Germany
4. IPSI, NYCU, Hsinchu, Taiwan
Funder
Research Center on Advanced Memory and Computing
IoE scheme at the IIT Madras
European Union's ECSEL
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
http://xplorestaging.ieee.org/ielx7/7729/10016255/10184149.pdf?arnumber=10184149
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2. An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at ${\rm VDD}=$ 0 V Achieving Zero Leakage With ${<}$ 400-ns Wakeup Time for ULP Applications
3. Asymmetric Resistive Switching of Bilayer HfOx/AlOy and AlOy/HfOx Memristors: The Oxide Layer Characteristics and Performance Optimization for Digital Set and Analog Reset Switching
4. A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
5. Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
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